TY - GEN
T1 - Efficient LU factorization on FPGA-based machines
AU - Wang, Xiaofang
AU - Ziavras, Sotirios G.
AU - Savir, Jacob
PY - 2003
Y1 - 2003
N2 - Configurable computing has demonstrated its ability to significantly improve performance for many computationintensive applications. With steady advances in silicon technology, Field-Programmable Gate Array (FPGA) technologies have enabled the implementation of robust System-On-a-Programmable-Chip (SOPC) computing platforms, which, in turn, have given significant boost to the field of (re)configurable computing. With innovative approaches, it is now possible to implement various specialized parallel computing machines in FPGAs. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. We describe here our design and implementation of a parallel machine on an SOPC development board, using multiple copies of the Altera® soft configurable processor, namely Nios®; we use this design for the LU factorization of large, sparse matrices. Such matrices are ubiquitous in several application areas, including electrical power flow. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA-based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our FPGA-based approach.
AB - Configurable computing has demonstrated its ability to significantly improve performance for many computationintensive applications. With steady advances in silicon technology, Field-Programmable Gate Array (FPGA) technologies have enabled the implementation of robust System-On-a-Programmable-Chip (SOPC) computing platforms, which, in turn, have given significant boost to the field of (re)configurable computing. With innovative approaches, it is now possible to implement various specialized parallel computing machines in FPGAs. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. We describe here our design and implementation of a parallel machine on an SOPC development board, using multiple copies of the Altera® soft configurable processor, namely Nios®; we use this design for the LU factorization of large, sparse matrices. Such matrices are ubiquitous in several application areas, including electrical power flow. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA-based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our FPGA-based approach.
KW - FPGA
KW - LU factorization
KW - Matrix inversion
KW - Parallel processing
KW - SOPC
UR - http://www.scopus.com/inward/record.url?scp=1542726559&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=1542726559&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:1542726559
SN - 0889863350
SN - 9780889863354
T3 - Proceedings of the IASTED Multi-Conference- Power and Energy Systems
SP - 459
EP - 464
BT - Proceedings of the Seventh IASTED International Multi-Conference - Power and Energy Systems
A2 - Smedley, K.M.
T2 - Proceedings of the Seventh IASTED International Multi-Conference - Power and Energy Systems
Y2 - 24 February 2003 through 26 February 2003
ER -