Electrical characterization of dry and wet processed interface layer in Ge/high-K devices

Y. Ding, Durgamadhab Misra, M. N. Bhuyian, K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, G. J. Leusink

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Even through Ge/high-k interface has been extensively studied, the high leakage current associated with these gate stacks and interface defects continue to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). In this work, the dry and wet processed interface layers for three different p type Ge/High-K samples on 300 mm wafers were studied at different low temperatures by CV and GV measurement. Since low temperature measurements are more reliable several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are reported and interface quality is being discussed.

Original languageEnglish (US)
Title of host publicationSemiconductors, Dielectrics, and Metals for Nanoelectronics 13
EditorsS. Kar, D. Misra, K. Kita, D. Landheer
PublisherElectrochemical Society Inc.
Pages313-322
Number of pages10
Edition5
ISBN (Electronic)9781607685395
DOIs
StatePublished - Jan 1 2015
EventSymposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 13 - 228th ECS Meeting - Phoenix, United States
Duration: Oct 11 2015Oct 15 2015

Publication series

NameECS Transactions
Number5
Volume69
ISSN (Print)1938-6737
ISSN (Electronic)1938-5862

Other

OtherSymposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 13 - 228th ECS Meeting
CountryUnited States
CityPhoenix
Period10/11/1510/15/15

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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