This paper investigates the electrical characteristics at low temperatures through C-V, I-V and conductance measurements to understand the interface trap density behavior of Ti-Au/HfO2/p-GaAs gate stack. Room temperature interface state density, At, estimated for as-deposited Ti-Au/HfO 2/GaAs capacitors was found to be 3.68×1011cm -2eV-1. Low temperature measurement suggests that only fast interface states contribute to the conduction process. Devices subjected to a post-metal annealing at 90°C degraded further. When the characteristics of two different metal gates were compared, the accumulation capacitance density observed to be 1.4 fF/μm2 and 8.98 fF/μm2 for Be-Au/HfO2/GaAs and Ti-Au/HfO2/GaAs respectively at 1 MHz. After annealing, the value of capacitance density decreased significantly mainly because of reduction in dielectric constant.