Abstract
As an emerging post-CMOS Field Effect Transistor, magneto-electric field-effect transistors (MEFETs) offer compelling design characteristics for logic and memory applications, such as high-speed switching, low power consumption, and nonvolatility. In this article, for the first time, a nonvolatile MEFET-based SRAM design named ME-SRAM is proposed for edge applications which can remarkably save the SRAM static power consumption in the idle state through a fast backup-restore process. To enable normally- OFF in situ computing, the ME-SRAM cell is integrated into a novel processing-in-SRAM architecture that exploits a hardware-optimized bitline computing approach for the execution of Boolean logic operations between operands housed in a memory sub-array within a single clock cycle. Our device-to-architecture evaluation results on Binary convolutional neural network acceleration show the robust performance of ME-SRAM while reducing energy consumption on average by a factor of compared to the best in-SRAM designs.
Original language | English (US) |
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Article number | 10440020 |
Pages (from-to) | 2742-2748 |
Number of pages | 7 |
Journal | IEEE Transactions on Electron Devices |
Volume | 71 |
Issue number | 4 |
DOIs | |
State | Published - Apr 1 2024 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Keywords
- Magneto-electric field-effect transistor (MEFET)
- normally-OFF computing
- processing-in-SRAM