TY - GEN
T1 - Event-Driven Spatiotemporal Processing-In-Sensor with Phase Change Memory-based Optical Acceleration
AU - Morsali, Mehrdad
AU - Najafi, Deniz
AU - Shafiee, Amin
AU - Tabrizchi, Sepehr
AU - Mercati, Pietro
AU - Imani, Mohsen
AU - Roohi, Arman
AU - Khoshavi, Navid
AU - Nikdast, Mahdi
AU - Angizi, Shaahin
N1 - Publisher Copyright:
© 2025 Copyright held by the owner/author(s).
PY - 2025/6/29
Y1 - 2025/6/29
N2 - This work introduces a novel hybrid electronic-optical processing-in-sensor architecture designed for low-cost, real-time frame processing at the edge. The proposed system enables event detection and integrates a TinyLSTM-based temporal inference model to analyze multiple frames in real time, extracting meaningful spatiotemporal features that trigger an address actuator for region-of-interest selection. By selectively reading out only relevant pixel regions, the architecture significantly reduces data transfer overhead and power consumption. Additionally, it harnesses the efficiency of silicon photonic (SiPh) devices to enable adaptive frame compression techniques and perform convolution operations through intrinsic, conversion-free multiply-accumulate computations. Device-to-architecture simulation results demonstrate 11.2 × improvement in performance compared to the state-of-the-art SiPh accelerator achieving 37 KFPS/W. This marks a significant advancement in processing-in-sensor technology, enhancing both computational efficiency and energy savings for edge AI applications.
AB - This work introduces a novel hybrid electronic-optical processing-in-sensor architecture designed for low-cost, real-time frame processing at the edge. The proposed system enables event detection and integrates a TinyLSTM-based temporal inference model to analyze multiple frames in real time, extracting meaningful spatiotemporal features that trigger an address actuator for region-of-interest selection. By selectively reading out only relevant pixel regions, the architecture significantly reduces data transfer overhead and power consumption. Additionally, it harnesses the efficiency of silicon photonic (SiPh) devices to enable adaptive frame compression techniques and perform convolution operations through intrinsic, conversion-free multiply-accumulate computations. Device-to-architecture simulation results demonstrate 11.2 × improvement in performance compared to the state-of-the-art SiPh accelerator achieving 37 KFPS/W. This marks a significant advancement in processing-in-sensor technology, enhancing both computational efficiency and energy savings for edge AI applications.
KW - Deep Neural Networks
KW - Processing-In-Sensor
KW - Silicon Photonics
KW - Vision Sensors
UR - https://www.scopus.com/pages/publications/105017628490
UR - https://www.scopus.com/pages/publications/105017628490#tab=citedBy
U2 - 10.1145/3716368.3735243
DO - 10.1145/3716368.3735243
M3 - Conference contribution
AN - SCOPUS:105017628490
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 1
EP - 7
BT - GLSVLSI 2025 - Proceedings of the Great Lakes Symposium on VLSI 2025
PB - Association for Computing Machinery
T2 - 35th Edition of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025
Y2 - 30 June 2025 through 2 July 2025
ER -