Exploiting mixed-mode parallelism for matrix operations on the HERA architecture through reconfiguration

Mathematics

• Reconfigurable Architectures 100%
• Mixed Mode 67%
• Reconfiguration 66%
• Parallelism 53%
• Architecture 52%
• Field Programmable Gate Array 31%
• LU Factorization 18%
• Floating point 16%
• Reconfigurable Computing 14%
• Unit 9%
• High Performance 8%
• Chip 8%
• Parallel Systems 8%
• Hardware 8%
• Matrix multiplication 7%
• Block Matrix 7%
• Diagonal matrix 7%
• Speedup 7%
• Complex Systems 6%
• Scheduling 6%
• Community 6%
• Experimental Results 6%
• Logic 5%

Engineering & Materials Science

• Reconfigurable architectures 62%
• Field programmable gate arrays (FPGA) 38%
• Factorization 31%
• Scheduling 10%
• Data storage equipment 9%
• Computer hardware 9%