TY - GEN
T1 - FPGA and ASIC square root designs for high performance and power efficiency
AU - Suresh, Shashank
AU - Beldianu, Spiridon F.
AU - Ziavras, Sotirios G.
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - Floating-point square root is a fundamental operation in signal processing and various HPC applications. Since this is an expensive operation in resource and energy consumption, its efficient implementation should be of priority in future multicores that will face dark silicon issues. This paper presents a low-cost, low-power consumption design to calculate the square root using the IEEE754 single-precision floating-point format. Two versions of the design are investigated with and without clock gating (CG), respectively. Evaluation involves FPGA and ASIC technologies at 40 and 65 nm. Substantial performance growth and reduced power consumption are gained as compared to a popular iterative solution. The ASIC design demonstrates much lower power consumption, which at 40 nm is lower than that at 65 nm by about a threefold. At 40 nm, CG for the ASIC realization is justified primarily for low activity rates.
AB - Floating-point square root is a fundamental operation in signal processing and various HPC applications. Since this is an expensive operation in resource and energy consumption, its efficient implementation should be of priority in future multicores that will face dark silicon issues. This paper presents a low-cost, low-power consumption design to calculate the square root using the IEEE754 single-precision floating-point format. Two versions of the design are investigated with and without clock gating (CG), respectively. Evaluation involves FPGA and ASIC technologies at 40 and 65 nm. Substantial performance growth and reduced power consumption are gained as compared to a popular iterative solution. The ASIC design demonstrates much lower power consumption, which at 40 nm is lower than that at 65 nm by about a threefold. At 40 nm, CG for the ASIC realization is justified primarily for low activity rates.
KW - ASIC
KW - FPGA
KW - energy consumption
KW - floating-point square root
KW - multicore processors
UR - http://www.scopus.com/inward/record.url?scp=84883368478&partnerID=8YFLogxK
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U2 - 10.1109/ASAP.2013.6567588
DO - 10.1109/ASAP.2013.6567588
M3 - Conference contribution
AN - SCOPUS:84883368478
SN - 9781479904921
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 269
EP - 272
BT - ASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
T2 - 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013
Y2 - 5 June 2013 through 7 June 2013
ER -