TY - GEN

T1 - FPGA-based normalization for Modified Gram-Schmidt Orthogonalization

AU - Sajid, I.

AU - Ziavras, Sotirios G.

AU - Ahmed, M. M.

PY - 2010

Y1 - 2010

N2 - Eigen values evaluation is an integral but computation-intensive part for many image and signal processing applications. Modified Gram-Schmidt Orthogonalization (MGSO) is an efficient method for evaluating the Eigen values in face recognition algorithms. MGSO applies normalization of vectors in its iterative orthogonal process and its accuracy depends on the accuracy of normalization. Using software, floatingpoint data types and floating-point operations are applied to minimize rounding and truncation effects. Hardware support for floating-point operations may be very costly in execution time per operation and also may increase power consumption. In contrast, lower-cost fixed-point arithmetic reduces execution times and lowers the power consumption but reduces slightly the precision. Normalization involves square root operations in addition to other arithmetic operations. Hardware realization of the floating-point square root operation may be prohibitively expensive because of its complexity. This paper presents three architectures, namely ppc405, ppc-ip and pc-pci, that employ fixed-point hardware for the efficient implementation of normalization on an FPGA. We evaluate the suitability of these architectures based on the needed frequency of normalization. The proposed architectures produce a less than 10-3 error rate compared with their software-driven counterpart for implementing floating-point operations. Furthermore, four popular databases of faces are used to benchmark the proposed architectures.

AB - Eigen values evaluation is an integral but computation-intensive part for many image and signal processing applications. Modified Gram-Schmidt Orthogonalization (MGSO) is an efficient method for evaluating the Eigen values in face recognition algorithms. MGSO applies normalization of vectors in its iterative orthogonal process and its accuracy depends on the accuracy of normalization. Using software, floatingpoint data types and floating-point operations are applied to minimize rounding and truncation effects. Hardware support for floating-point operations may be very costly in execution time per operation and also may increase power consumption. In contrast, lower-cost fixed-point arithmetic reduces execution times and lowers the power consumption but reduces slightly the precision. Normalization involves square root operations in addition to other arithmetic operations. Hardware realization of the floating-point square root operation may be prohibitively expensive because of its complexity. This paper presents three architectures, namely ppc405, ppc-ip and pc-pci, that employ fixed-point hardware for the efficient implementation of normalization on an FPGA. We evaluate the suitability of these architectures based on the needed frequency of normalization. The proposed architectures produce a less than 10-3 error rate compared with their software-driven counterpart for implementing floating-point operations. Furthermore, four popular databases of faces are used to benchmark the proposed architectures.

KW - FPGA

KW - Modified Gram-Schmidt

KW - Normalization

KW - Orthogonalization

UR - http://www.scopus.com/inward/record.url?scp=77956326389&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77956326389&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:77956326389

SN - 9789896740283

T3 - VISAPP 2010 - Proceedings of the International Conference on Computer Vision Theory and Applications

SP - 227

EP - 232

BT - VISAPP 2010 - Proceedings of the International Conference on Computer Vision Theory and Applications

T2 - 5th International Conference on Computer Vision Theory and Applications, VISAPP 2010

Y2 - 17 May 2010 through 21 May 2010

ER -