FPGA-based vector processing for matrix operations

Yang Hongyan, Sotirios G. Ziavras, Hu Jie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor is implemented on the Xilinx XC2V6000-5 FPGA chip. To test the performance, the W-matrix sparse solver for linear equations is realized. W-matrix was first proposed for power flow analysis and is prone to parallel computing. We show that actual power matrices with up to 1723 nodes can be dealt with in less than 1.1ms on the FPGA. A comparison with a commercial PC indicates that the vector processor is competitive for such computation-intensive problems.

Original languageEnglish (US)
Title of host publicationProceedings - International Conference on Information Technology-New Generations, ITNG 2007
Pages989-994
Number of pages6
DOIs
StatePublished - Aug 28 2007
Event4th International Conference on Information Technology-New Generations, ITNG 2007 - Las Vegas, NV, United States
Duration: Apr 2 2007Apr 4 2007

Publication series

NameProceedings - International Conference on Information Technology-New Generations, ITNG 2007

Other

Other4th International Conference on Information Technology-New Generations, ITNG 2007
Country/TerritoryUnited States
CityLas Vegas, NV
Period4/2/074/4/07

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Information Systems
  • Software

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