FPGA-based vector processor for algebraic equation solvers

Hongyan Yang; Sotirios Ziavras

FPGA-based vector processor for algebraic equation solvers

Hongyan Yang, Sotirios Ziavras

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference, 2005 SOCC
Editors	D. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages	115-116
Number of pages	2
State	Published - Dec 1 2005
Event	2005 IEEE International SOC Conference - Herndon, VA, United States Duration: Sep 25 2005 → Sep 28 2005

Other

Other	2005 IEEE International SOC Conference
Country/Territory	United States
City	Herndon, VA
Period	9/25/05 → 9/28/05

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

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title = "FPGA-based vector processor for algebraic equation solvers",

abstract = "In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.",

author = "Hongyan Yang and Sotirios Ziavras",

year = "2005",

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note = "2005 IEEE International SOC Conference ; Conference date: 25-09-2005 Through 28-09-2005",

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AU - Yang, Hongyan

AU - Ziavras, Sotirios

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N2 - In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.

AB - In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.

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M3 - Conference contribution

AN - SCOPUS:30844470443

SN - 0780392647

SN - 9780780392649

SP - 115

EP - 116

BT - Proceedings - IEEE International SOC Conference, 2005 SOCC

A2 - Ha, D.

A2 - Krishnamurthy, R.

A2 - Kim, S.

A2 - Marshall, A.

T2 - 2005 IEEE International SOC Conference

Y2 - 25 September 2005 through 28 September 2005

ER -

FPGA-based vector processor for algebraic equation solvers

Abstract

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All Science Journal Classification (ASJC) codes

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