Abstract
In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International SOC Conference, 2005 SOCC |
Editors | D. Ha, R. Krishnamurthy, S. Kim, A. Marshall |
Pages | 115-116 |
Number of pages | 2 |
State | Published - Dec 1 2005 |
Event | 2005 IEEE International SOC Conference - Herndon, VA, United States Duration: Sep 25 2005 → Sep 28 2005 |
Other
Other | 2005 IEEE International SOC Conference |
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Country/Territory | United States |
City | Herndon, VA |
Period | 9/25/05 → 9/28/05 |
All Science Journal Classification (ASJC) codes
- Engineering(all)