FPGA-based vector processor for algebraic equation solvers

Hongyan Yang, Sotirios Ziavras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages115-116
Number of pages2
StatePublished - Dec 1 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: Sep 25 2005Sep 28 2005

Other

Other2005 IEEE International SOC Conference
CountryUnited States
CityHerndon, VA
Period9/25/059/28/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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