FPGA implementation of a cholesky algorithm for a shared-memory multiprocessor architecture

Keyphrases

• Field Programmable Gate Array Implementation 100%
• Shared-memory multiprocessors 100%
• Multiprocessor Architecture 100%
• Cholesky Algorithm 100%
• Altera 100%
• Dynamic Load Balancing 66%
• Cholesky 66%
• Matrix Factorization 66%
• System Use 33%
• Commercially Available 33%
• Field Programmable Gate Arrays 33%
• Parallel Machines 33%
• Shared Memory 33%
• Multiprocessor 33%
• Matrix Operation 33%
• Performance Results 33%
• Development Environment 33%
• Processing Element 33%
• Programmable System-on-Chip (PSoC) 33%
• Load Balancing Algorithm 33%
• System of Linear Equations 33%
• Task-based Approach 33%
• Processor Core 33%
• Quartus II 33%
• Nios 33%
• Single-chip multiprocessors 33%
• Uniprocessor 33%
• Large Institutions 33%
• Parallel Version 33%
• Multiprocessor Systems 33%
• Multiprocessor Implementation 33%
• Dense Matrix 33%
• Matrix Factorization Algorithm 33%
• Benefits Matrix 33%

Computer Science

• Field Programmable Gate Arrays 100%
• Matrix Factorization 100%
• Shared Memory Multiprocessor 100%
• multi-processor 66%
• Dynamic Load Balancing 66%
• Linear Equation 33%
• Supercomputer 33%
• Parallel Machine 33%
• Shared Memories 33%
• MIMD 33%
• Matrix Operation 33%
• Development Environment 33%
• Processing Element 33%
• Factorization Process 33%
• single-chip 33%
• Processor Core 33%
• Factorization Algorithm 33%
• Chip Multiprocessor 33%
• Parallel Version 33%
• Multiprocessor System 33%