Gate-dielectric interface effects on low-frequency (1/f) noise in p-MOSFETs with high-K dielectrics

P. Srinivasan, E. Simoen, R. Singanamalla, H. Y. Yu, C. Claeys, D. Misra

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Introduction: Aggressive scaling of MOSFETs has led to the implementation of Hf-based high-K dielectric materials as an alternative to SiO2 gate oxides for CMOS technologies. Metal-gate and FUSI electrode materials, due to reduced poly-depletion and remote scattering effects, are considered for replacing poly-Si gate electrodes. These changes are seen to have a fundamental impact on 1/f noise performance [1]. For the first time, we show that the 1/f noise is affected by the gate-dielectric interface. This is done by studying poly-Si, metal and undoped FUlly nickel Sllicided (FUSI) gate electrodes on pure SiON, Hf-silicate and HfO2 dielectric p-MOSFETs. Results and Discussion: The noise was measured on 10 μm × 1 μm p-MOSFETs in linear (|VDS| = 0.05 V) regime with the gate bias changed from weak to strong inversion. EOT of the devices is 1.5nm±0.2nm. Fig. 1 shows the ID-VG and GM-VG characteristics of TiN-TaN (metal), poly-Si, NiSi (FUSI) gate electrodes on 55% Hf-silicate gate dielectrics. A higher VT shift and lower GM is observed for poly-Si MOSFETs while metal and FUSI performances are quite comparable, which is mainly attributed to work-function shift of the gate electrode material. Figs 2, 3 and 4 represent the f × Si Vs frequency f at |V G - VT| ∼ 0.1 V, for the p-MOSFETs with the different gate electrode materials studied, with every plot showing the performance for various Hf-silicate %. f × SI spectra are also compared with the tunneling distance z along the second X-axis, with the lowest frequency [2] corresponding to the gate electrode-dielectric interface. It is also noted that these spectra roughly correlate with trap density profiles in the oxide, though accurate CET values need to be considered. The impact due to the gates is clearly observed, with metal gates [Fig. 2] showing a higher value near the gate-dielectric interface, while it is constant and has a lower value in the bulk oxide. However, the poly-Si profile shows a constant value throughout the oxide and also at the interface. In the case of FUSI gates, the lowest values were seen to be at the gate-dielectric interface [2] while higher values are seen towards the substrate-dielectric interface. It is also clear that the frequency exponent γ in 1/f changes with f as γ ∼ 1 for poly-Si, γ>1 for TiN-TaN while for FUSI it is γ < 1 [not shown]. SI-ID characteristics were also plotted for these gate electrodes for 55% Hf-silicates as shown in Fig. 5. The drain current noise is found to be lower for FUSI and metal gates when compared to poly-Si, which correlates with the GM and VT of the devices in Fig. 1. The input-referred noise values in Fig. 6 were also seen to follow the same trend when the effect of GM was normalized. For FUSI gates, the noise was also studied as a function of the percentage Hf. From the S I-ID characteristics in Fig. 7, it looks like that this parameter has little or no effect on the 1/f noise. This is confirmed by the input referred noise of Fig. 8 showing a very weak or no dependence on Hf content while the reference SiON has comparatively lower values. Combining the results of all the samples in the SVG Vs % Hf plot at |VG-V T| ∼ 0.15 of Fig. 9, the values are seen to be more or less comparable, where there is a weak or no correlation between the Hf-content and 1/f noise magnitude. Conclusion: In conclusion, it is seen that the gate-dielectric interface has a strong impact on the LF noise properties when poly-Si, metal and FUSI gates are studied in p-MOSFET Hf-silicate devices. The study of the Hf/Si percentage on the 1/f noise of FUSI gate devices reveals comparable values of noise performance, indicating a weak or no dependence on the Hf content. The existing models do not take these gate-dielectric interface effects into account, but should clearly be considered in the future. Acknowledgements: The authors would like to thank L. Pantisano and IMEC's high-k group for stimulating discussions. P. Srinivasan acknowledges NSF (Award# ECS 0140584) for partial financial support.

Original languageEnglish (US)
Title of host publication2005 International Semiconductor Device Research Symposium
Number of pages2
StatePublished - 2005
Event2005 International Semiconductor Device Research Symposium - Bethesda, MD, United States
Duration: Dec 7 2005Dec 9 2005

Publication series

Name2005 International Semiconductor Device Research Symposium


Other2005 International Semiconductor Device Research Symposium
Country/TerritoryUnited States
CityBethesda, MD

All Science Journal Classification (ASJC) codes

  • General Engineering


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