Generator choices for delay test

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Abstract

An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility.

Original languageEnglish (US)
Pages (from-to)214-221
Number of pages8
JournalProceedings of the Asian Test Symposium
StatePublished - Dec 1 1995
Externally publishedYes
EventProceedings of the 1995 4th Asian Test Symposium - Bangalore, India
Duration: Nov 23 1995Nov 24 1995

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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