HARDWARE IMPLEMENTATION OF A MULTI-RATE REAL-TIME SPEECH CODEC

Bruce Bukiet; Roderick J. Ragland; John Damoulakis

HARDWARE IMPLEMENTATION OF A MULTI-RATE REAL-TIME SPEECH CODEC

Bruce Bukiet
, Roderick J. Ragland
, John Damoulakis

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes a multi-rate voice coder/decoder which is totally self contained and portable, requiring only an outlet to a standard North American 110 VAC power line. Virtually everything needed to perform speech coding experiments is contained within the instrument case. This system employs the INTEL 8751 micro-controller and two digital signal processors: the Texas Instrument TMS320 for data acquisition and the AT&T DSP32 for speech coding. The speech coding repertoire includes the following algorithms: o 400 bps vector quantized LPC o 800 bps vector quantized LPC o 2800 bps scalar quantized LPC o 10500 bps residual excited LPC o 32000 bps ADPCM Both the hardware and software configurations are described, along with measured execution times and program and data memory usages. A review of the coding algorithms is presented, with a brief summary of the system's operational parameters.

Original language	English (US)
Pages	2033-2036
Number of pages	4
State	Published - 1987
Externally published	Yes
Event	1987 European Conference on Speech Technology, ECST 1987 - Edinburgh, United Kingdom Duration: Sep 1 1987 → Sep 4 1987

Conference

Conference	1987 European Conference on Speech Technology, ECST 1987
Country/Territory	United Kingdom
City	Edinburgh
Period	9/1/87 → 9/4/87

All Science Journal Classification (ASJC) codes

Language and Linguistics
Computer Vision and Pattern Recognition
Human-Computer Interaction
Software
Linguistics and Language

Cite this

@conference{b89cb8b274ad43e68ec53bbd0b464965,

title = "HARDWARE IMPLEMENTATION OF A MULTI-RATE REAL-TIME SPEECH CODEC",

abstract = "This paper describes a multi-rate voice coder/decoder which is totally self contained and portable, requiring only an outlet to a standard North American 110 VAC power line. Virtually everything needed to perform speech coding experiments is contained within the instrument case. This system employs the INTEL 8751 micro-controller and two digital signal processors: the Texas Instrument TMS320 for data acquisition and the AT\&T DSP32 for speech coding. The speech coding repertoire includes the following algorithms: o 400 bps vector quantized LPC o 800 bps vector quantized LPC o 2800 bps scalar quantized LPC o 10500 bps residual excited LPC o 32000 bps ADPCM Both the hardware and software configurations are described, along with measured execution times and program and data memory usages. A review of the coding algorithms is presented, with a brief summary of the system's operational parameters.",

author = "Bruce Bukiet and Ragland, \{Roderick J.\} and John Damoulakis",

note = "Publisher Copyright: {\textcopyright} European Conference on Speech Technology, ECST 1987. All rights reserved.; 1987 European Conference on Speech Technology, ECST 1987 ; Conference date: 01-09-1987 Through 04-09-1987",

year = "1987",

language = "English (US)",

pages = "2033--2036",

}

TY - CONF

T1 - HARDWARE IMPLEMENTATION OF A MULTI-RATE REAL-TIME SPEECH CODEC

AU - Bukiet, Bruce

AU - Ragland, Roderick J.

AU - Damoulakis, John

PY - 1987

Y1 - 1987

N2 - This paper describes a multi-rate voice coder/decoder which is totally self contained and portable, requiring only an outlet to a standard North American 110 VAC power line. Virtually everything needed to perform speech coding experiments is contained within the instrument case. This system employs the INTEL 8751 micro-controller and two digital signal processors: the Texas Instrument TMS320 for data acquisition and the AT&T DSP32 for speech coding. The speech coding repertoire includes the following algorithms: o 400 bps vector quantized LPC o 800 bps vector quantized LPC o 2800 bps scalar quantized LPC o 10500 bps residual excited LPC o 32000 bps ADPCM Both the hardware and software configurations are described, along with measured execution times and program and data memory usages. A review of the coding algorithms is presented, with a brief summary of the system's operational parameters.

AB - This paper describes a multi-rate voice coder/decoder which is totally self contained and portable, requiring only an outlet to a standard North American 110 VAC power line. Virtually everything needed to perform speech coding experiments is contained within the instrument case. This system employs the INTEL 8751 micro-controller and two digital signal processors: the Texas Instrument TMS320 for data acquisition and the AT&T DSP32 for speech coding. The speech coding repertoire includes the following algorithms: o 400 bps vector quantized LPC o 800 bps vector quantized LPC o 2800 bps scalar quantized LPC o 10500 bps residual excited LPC o 32000 bps ADPCM Both the hardware and software configurations are described, along with measured execution times and program and data memory usages. A review of the coding algorithms is presented, with a brief summary of the system's operational parameters.

UR - https://www.scopus.com/pages/publications/85135085115

UR - https://www.scopus.com/pages/publications/85135085115#tab=citedBy

M3 - Paper

AN - SCOPUS:85135085115

SP - 2033

EP - 2036

T2 - 1987 European Conference on Speech Technology, ECST 1987

Y2 - 1 September 1987 through 4 September 1987

ER -

HARDWARE IMPLEMENTATION OF A MULTI-RATE REAL-TIME SPEECH CODEC

Abstract

Conference

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this