HERA: A reconfigurable and mixed-mode parallel computing engine on platform FPGAs

Xiaofang Wang, Sotirios G. Ziavras

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations

Abstract

The high price, long design and development cycles, programming difficulty and high maintenance cost of supercomputers limit their range of potential applications. Recent advances in Field-Programmable Gate Arrays (FPGAs) have made feasible the development of high-performance and programmable parallel systems on a programmable chip (PSOPC). PSOPC's yield high-performance at low cost for many parallel applications. We present in this paper the design and implementation of our HERA (HEterogeneous Reconfigurable Architecture) machine that employs FPGAs to allow the simultaneous execution of a variety of parallel processing modes, including SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, Multiple-Data) and M-SIMD (Multiple-SIMD). The processing element is centered on a single-precision IEEE 754 floating-point unit (FPU) and employs a 7-stage pipeline. To demonstrate the robustness and viability of our approach, we propose a data partitioning scheme and employ mixed-mode scheduling for Cannon's matrix-matrix multiplication algorithm with matrices of arbitrary size and shape. Performance results on our 64-PE machine that employs a dual-FPGA system are better than the optimized performance on a dual-Xeon PC.

Original languageEnglish (US)
Article number439-158
Pages (from-to)374-379
Number of pages6
JournalProceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems
Volume16
StatePublished - Dec 1 2004
EventProceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems - Cambridge, MA, United States
Duration: Nov 9 2004Nov 11 2004

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

Keywords

  • Cannon's algorithm
  • Floating-point arithmetic
  • Matrix multiplication
  • Parallel processing
  • Reconfigurable architecture
  • SIMD/MIMD mixed-mode computing

Fingerprint

Dive into the research topics of 'HERA: A reconfigurable and mixed-mode parallel computing engine on platform FPGAs'. Together they form a unique fingerprint.

Cite this