Gate stack engineering for advanced deep submicron CMOS technology nodes has been extensively studied during the last decade, so that high-κ dielectrics in combination with metal gate or FUSI electrodes are implemented in several research lines. Much effort has been concentrated on the optimization of gate stacks from a viewpoint of dielectric properties and reliability issues. Less information is available on the low frequency noise performance of these gate stacks, which is an essential parameter for both analog and mixed signal applications. This review demonstrates the necessity of gate stack engineering for achieving a low 1/f noise performance. The impact of several processing parameters, such as the thickness of the interfacial layer and the high-κ oxide, bulk properties of the high-κ layer, post deposition anneal (PDA) treatments, choice of gate electrode material (poly-silicon, fully suicided or metal) will be addressed in order to point out the role of the different interfaces and bulk layers of the gate stack. Such a systematic study will form the basis for noise modeling as for these gate-dielectrics the standard noise models are no longer applicable. Finally, the impact on the noise behavior of strain engineering in the silicon substrate to boost up the carrier mobility is briefly discussed. Copyright The Electrochemical Society.