TY - GEN
T1 - HiRISE
T2 - 61st ACM/IEEE Design Automation Conference, DAC 2024
AU - Reidy, Brendan
AU - Tabrizchi, Sepehr
AU - Mohammadi, Mohammadreza
AU - Angizi, Shaahin
AU - Roohi, Arman
AU - Zand, Ramtin
N1 - Publisher Copyright:
© 2024 Copyright held by the owner/author(s).
PY - 2024/11/7
Y1 - 2024/11/7
N2 - With the rise of tiny IoT devices powered by machine learning (ML), many researchers have directed their focus toward compressing models to fit on tiny edge devices. Recent works have achieved remarkable success in compressing ML models for object detection and image classification on microcontrollers with small memory, e.g., 512kB SRAM. However, there remain many challenges prohibiting the deployment of ML systems that require high-resolution images. Due to fundamental limits in memory capacity for tiny IoT devices, it may be physically impossible to store large images without external hardware. To this end, we propose a high-resolution image scaling system for edge ML, called HiRISE, which is equipped with selective region-of-interest (ROI) capability leveraging analog in-sensor image scaling. Our methodology not only significantly reduces the peak memory requirements, but also achieves up to 17.7× reduction in data transfer and energy consumption.
AB - With the rise of tiny IoT devices powered by machine learning (ML), many researchers have directed their focus toward compressing models to fit on tiny edge devices. Recent works have achieved remarkable success in compressing ML models for object detection and image classification on microcontrollers with small memory, e.g., 512kB SRAM. However, there remain many challenges prohibiting the deployment of ML systems that require high-resolution images. Due to fundamental limits in memory capacity for tiny IoT devices, it may be physically impossible to store large images without external hardware. To this end, we propose a high-resolution image scaling system for edge ML, called HiRISE, which is equipped with selective region-of-interest (ROI) capability leveraging analog in-sensor image scaling. Our methodology not only significantly reduces the peak memory requirements, but also achieves up to 17.7× reduction in data transfer and energy consumption.
UR - http://www.scopus.com/inward/record.url?scp=85205860688&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85205860688&partnerID=8YFLogxK
U2 - 10.1145/3649329.3656539
DO - 10.1145/3649329.3656539
M3 - Conference contribution
AN - SCOPUS:85205860688
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 23 June 2024 through 27 June 2024
ER -