TY - GEN
T1 - Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing
AU - Najafi, Deniz
AU - Tabrizchi, Sepehr
AU - Zhou, Ranyang
AU - Solouki, Mohammadreza Amel
AU - Marshal, Andrew
AU - Roohi, Arman
AU - Angizi, Shaahin
N1 - Publisher Copyright:
© 2024 Owner/Author.
PY - 2024/6/12
Y1 - 2024/6/12
N2 - The surge in the number of normally-off power-constraint Internet of Things (IoT) devices in recent years has amplified the demand for high-performance and energy-efficient in-memory computing architectures built on top of various non-volatile memories. Magneto-Electric Field Effect Transistors (MEFETs) have presented compelling design features suitable for logic and memory integration as an emerging post-CMOS FET. These include high-speed switching, minimal power usage, and non-volatility. This work introduces a new in-memory computing architecture designed for edge applications, leveraging emerging MEFETs. The proposed architecture enables the execution of both Boolean logic operations and Binary Content Addressable Memory (BCAM) operations within a single cycle. Furthermore, the energy consumption during the write operation of the proposed cell is optimized by introducing a new write circuitry. The outcomes of our device-to-architecture evaluation reveal approximately 43.5% and 96.9% reduction in read and write energy consumption, respectively, compared to the counterpart non-volatile memories. At the application level, the proposed architecture is applied to implement Binary Neural Networks (BNNs) based on AlexNet and VGG16. Our results showcase a decrease of approximately 54% in the overall energy consumption when implementing these networks using the proposed design compared to non-volatile in-memory computing designs.
AB - The surge in the number of normally-off power-constraint Internet of Things (IoT) devices in recent years has amplified the demand for high-performance and energy-efficient in-memory computing architectures built on top of various non-volatile memories. Magneto-Electric Field Effect Transistors (MEFETs) have presented compelling design features suitable for logic and memory integration as an emerging post-CMOS FET. These include high-speed switching, minimal power usage, and non-volatility. This work introduces a new in-memory computing architecture designed for edge applications, leveraging emerging MEFETs. The proposed architecture enables the execution of both Boolean logic operations and Binary Content Addressable Memory (BCAM) operations within a single cycle. Furthermore, the energy consumption during the write operation of the proposed cell is optimized by introducing a new write circuitry. The outcomes of our device-to-architecture evaluation reveal approximately 43.5% and 96.9% reduction in read and write energy consumption, respectively, compared to the counterpart non-volatile memories. At the application level, the proposed architecture is applied to implement Binary Neural Networks (BNNs) based on AlexNet and VGG16. Our results showcase a decrease of approximately 54% in the overall energy consumption when implementing these networks using the proposed design compared to non-volatile in-memory computing designs.
UR - http://www.scopus.com/inward/record.url?scp=85197948535&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85197948535&partnerID=8YFLogxK
U2 - 10.1145/3649476.3660361
DO - 10.1145/3649476.3660361
M3 - Conference contribution
AN - SCOPUS:85197948535
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 770
EP - 775
BT - GLSVLSI 2024 - Proceedings of the Great Lakes Symposium on VLSI 2024
PB - Association for Computing Machinery
T2 - 34th Great Lakes Symposium on VLSI 2024, GLSVLSI 2024
Y2 - 12 June 2024 through 14 June 2024
ER -