TY - GEN
T1 - Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device
AU - Parveen, Farhana
AU - Angizi, Shaahin
AU - He, Zhezhi
AU - Fan, Deliang
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - Polymorphic gates are capable of adapting to multiple functionalities depending on the application and need. In this paper, we propose a hybrid spin-CMOS polymorphic logic gate based on a novel 6 terminal composite magnetic domain wall motion device structure. As far as we know, we are the first to present a single polymorphic gate that is able to perform a full set of 2-input Boolean logic functions (i.e. AND/NAND, OR/NOR, NOT, XOR/XNOR) by configuring the applied keys. The SPICE device-circuit co-simulation indicates that a full adder design using our proposed polymorphic logic gate shows 45.74% power reduction compared with traditional CMOS full adder design. Moreover, it can be a promising hardware security primitive by implementing logic locking and polymorphic transformation to protect Integrated Circuit (IC) against counterfeiting and reverse engineering. To summarize, our proposed design simultaneously provides non-volatility, low power consumption, compactness and polymorphism to logic circuits, which opens a new paradigm for future power efficient and secured computing.
AB - Polymorphic gates are capable of adapting to multiple functionalities depending on the application and need. In this paper, we propose a hybrid spin-CMOS polymorphic logic gate based on a novel 6 terminal composite magnetic domain wall motion device structure. As far as we know, we are the first to present a single polymorphic gate that is able to perform a full set of 2-input Boolean logic functions (i.e. AND/NAND, OR/NOR, NOT, XOR/XNOR) by configuring the applied keys. The SPICE device-circuit co-simulation indicates that a full adder design using our proposed polymorphic logic gate shows 45.74% power reduction compared with traditional CMOS full adder design. Moreover, it can be a promising hardware security primitive by implementing logic locking and polymorphic transformation to protect Integrated Circuit (IC) against counterfeiting and reverse engineering. To summarize, our proposed design simultaneously provides non-volatility, low power consumption, compactness and polymorphism to logic circuits, which opens a new paradigm for future power efficient and secured computing.
KW - Polymorphic gate
KW - domain wall motion
KW - hardware security
KW - magnetic tunnel junction
KW - spintronics
UR - http://www.scopus.com/inward/record.url?scp=85032658822&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85032658822&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2017.8050921
DO - 10.1109/ISCAS.2017.8050921
M3 - Conference contribution
AN - SCOPUS:85032658822
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -