Abstract
An approach to implementing neural computing with Boolean programmable logic is presented. A technique for the implementation of image morphological operations using a neural architecture is developed. Image morphological operations, by their very nature, involve repeated computations over large data structures. Parallelism appears to be a necessary attribute of a hardware system which can efficiently perform such image analysis tasks.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 774-777 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| State | Published - 1989 |
| Event | IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, OR, USA Duration: May 8 1989 → May 11 1989 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering