Impact of constant voltage stress on high-κ gate dielectric for RF IC performance

P. C. Paliwoda, Durgamadhab Misra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Challenges in modem CMOS RF IC design include optimizing gain, noise and linearity. These parameters are highly dependent on transconductance (g m) and threshold voltage (V t). Introduction of high-κ dielectrics with metal gates in advanced CMOS gate stacks requires that the impact of any variation of g m and V t due to stress on RFIC performance needs to be investigated thoroughly. This paper investigates the effect of positive constant voltage stress (CVS) on device parameter degradation which may have a potential impact on analog and mixed-signal CMOS circuitry. Significant decrease in g m and increase in V t was observed under CVS due to electron trapping.

Original languageEnglish (US)
Title of host publicationPhysics and Technology of High-k Materials 9
Pages415-419
Number of pages5
Edition3
DOIs
StatePublished - Dec 1 2011
Event9th International Symposium on High Dielectric Constant and Other Dielectric Materials for Nanoelectronics and Photonics - 220th ECS Meeting - Boston, MA, United States
Duration: Oct 10 2011Oct 12 2011

Publication series

NameECS Transactions
Number3
Volume41
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other9th International Symposium on High Dielectric Constant and Other Dielectric Materials for Nanoelectronics and Photonics - 220th ECS Meeting
Country/TerritoryUnited States
CityBoston, MA
Period10/10/1110/12/11

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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