TY - GEN
T1 - Improving MLC PCM write throughput by write reconstruction
AU - Luo, Huizhang
AU - Shi, Liang
AU - Zhao, Mengying
AU - Zhuge, Qingfeng
AU - Xue, Chun Jason
N1 - Funding Information:
VII. Acknowledgment: This work is partially supported by the Fundamental Research Funds for the Central Universities (106112014CDJZR185502), NSFC 61402059, NSFC 61472052, NSFC 61173014, National 863 Program 2013AA013202, 2015AA015304, Chongqing High-Tech Research Program cstc2012ggC40005, cstc2014yykfB40007.
Publisher Copyright:
© 2015 IEEE.
PY - 2015/10/22
Y1 - 2015/10/22
N2 - The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and nonvolatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms Single-Level-Cell (SLC) in density. However, the high write latency is a performance bottleneck for MLC PCM for two reasons. First, MLC PCM has a much longer programming time. Second, the write latencies of different transitions of cell states range widely. When cells are concurrently written in burst mode, the write latency of a burst is decided by the worst one. To improve the write throughput of MLC PCM, this paper proposes a Write Reconstruction (WR) scheme. WR reconstructs multiple burst writes targeting the same row. The worst case cells are put together in some writes. By this way, the write latency of other writes will be reduced. WR incurs low implementation overhead and shows significant efficiency. Experimental results show that WR achieves 15.1% of write latency reduction on average, with negligible power overhead (3.4%).
AB - The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and nonvolatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms Single-Level-Cell (SLC) in density. However, the high write latency is a performance bottleneck for MLC PCM for two reasons. First, MLC PCM has a much longer programming time. Second, the write latencies of different transitions of cell states range widely. When cells are concurrently written in burst mode, the write latency of a burst is decided by the worst one. To improve the write throughput of MLC PCM, this paper proposes a Write Reconstruction (WR) scheme. WR reconstructs multiple burst writes targeting the same row. The worst case cells are put together in some writes. By this way, the write latency of other writes will be reduced. WR incurs low implementation overhead and shows significant efficiency. Experimental results show that WR achieves 15.1% of write latency reduction on average, with negligible power overhead (3.4%).
KW - Computer architecture
KW - Decoding
KW - Microprocessors
KW - Phase change materials
KW - Programming
KW - Resistance
KW - Sorting
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U2 - 10.1109/NVMSA.2015.7304373
DO - 10.1109/NVMSA.2015.7304373
M3 - Conference contribution
AN - SCOPUS:84962046035
T3 - 2015 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2015
BT - 2015 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2015
Y2 - 19 August 2015 through 21 August 2015
ER -