The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and nonvolatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms Single-Level-Cell (SLC) in density. However, the high write latency is a performance bottleneck for MLC PCM for two reasons. First, MLC PCM has a much longer programming time. Second, the write latencies of different transitions of cell states range widely. When cells are concurrently written in burst mode, the write latency of a burst is decided by the worst one. To improve the write throughput of MLC PCM, this paper proposes a Write Reconstruction (WR) scheme. WR reconstructs multiple burst writes targeting the same row. The worst case cells are put together in some writes. By this way, the write latency of other writes will be reduced. WR incurs low implementation overhead and shows significant efficiency. Experimental results show that WR achieves 15.1% of write latency reduction on average, with negligible power overhead (3.4%).