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Instruction Fusion for Multiscalar and Many-Core Processors
Yaojie Lu,
Sotirios G. Ziavras
Electrical and Computer Engineering
Graduate Studies
Office of the Provost
Research output
:
Contribution to journal
›
Article
›
peer-review
1
Scopus citations
Overview
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Dive into the research topics of 'Instruction Fusion for Multiscalar and Many-Core Processors'. Together they form a unique fingerprint.
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Computer Science
Many-Core
100%
Core Processor
100%
Instruction Cache
100%
Performance Gain
50%
Performance Improvement
50%
Benchmarking
50%
Fusion Technique
50%
Performance Degradation
50%
Memory Bandwidth
50%
Cache Hit Rate
50%
Instruction Memory
50%
Dynamic Power Dissipation
50%
Threshold Voltage
50%
Pipeline Stage
50%
Keyphrases
Many-core Processor
100%
Instruction Fusion
100%
Multi-scalar
100%
Instruction Cache
40%
Performance Improvement
20%
Performance Gain
20%
Code Size
20%
Program Implementation
20%
Multiple Cores
20%
Microprocessor
20%
Dynamic Power Dissipation
20%
Performance Degradation
20%
Memory Bandwidth
20%
Threshold Voltage
20%
FPGA Prototype
20%
Fusion Technique
20%
Cache Hit Ratio
20%
Program Size
20%
Utilization Wall
20%
Dual-core
20%
Voltage Scaling
20%
Targeted Application
20%
Multiple pipelines
20%
Vector Codes
20%
Pipeline Stages
20%
Similar Copy
20%
Instruction Memory
20%