Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

Durgamadhab Misra, N. A. Choudhury, R. Garg, P. Srinivasan

Research output: Contribution to conferencePaperpeer-review

4 Scopus citations

Abstract

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10 nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. In this paper some of the on-going research work on charge trapping will be reviewed. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO 2 and HfSiO 2 will be focused.

Original languageEnglish (US)
StatePublished - Dec 1 2004
EventIEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand
Duration: Nov 21 2004Nov 24 2004

Other

OtherIEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering
CountryThailand
CityChiang Mai
Period11/21/0411/24/04

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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