Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

D. Misra; N. A. Choudhury; R. Garg; P. Srinivasan

Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

D. Misra, N. A. Choudhury, R. Garg, P. Srinivasan

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

4 Scopus citations

Abstract

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10 nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. In this paper some of the on-going research work on charge trapping will be reviewed. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO ² and HfSiO ² will be focused.

Original language	English (US)
Pages	D320-D323
State	Published - 2004
Event	IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand Duration: Nov 21 2004 → Nov 24 2004

Other

Other	IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering
Country/Territory	Thailand
City	Chiang Mai
Period	11/21/04 → 11/24/04

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

Cite this

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title = "Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges",

abstract = "To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10 nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. In this paper some of the on-going research work on charge trapping will be reviewed. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO 2 and HfSiO 2 will be focused.",

author = "D. Misra and Choudhury, {N. A.} and R. Garg and P. Srinivasan",

year = "2004",

language = "English (US)",

pages = "D320--D323",

note = "IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering ; Conference date: 21-11-2004 Through 24-11-2004",

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Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges. / Misra, D.; Choudhury, N. A.; Garg, R. et al.
2004. D320-D323 Paper presented at IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering, Chiang Mai, Thailand.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Integration of high-K dielectrics into sub-65nm CMOS technology

T2 - IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering

AU - Misra, D.

AU - Choudhury, N. A.

AU - Garg, R.

AU - Srinivasan, P.

PY - 2004

Y1 - 2004

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AB - To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10 nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. In this paper some of the on-going research work on charge trapping will be reviewed. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO 2 and HfSiO 2 will be focused.

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ER -

Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

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All Science Journal Classification (ASJC) codes

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