Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

Keyphrases

• 65nm CMOS 100%
• Charge Trapping 33%
• Direct Tunneling 33%
• Gate Dielectric 33%
• Gate Length 33%
• Gate Stack 33%
• HfO2 33%
• HfSiO 33%
• High-k Dielectric 100%
• High-k Material 33%
• International Technology Roadmap for Semiconductors 33%
• Power Requirement 33%
• Reliability Constraint 33%
• Reliability Issues 33%
• Silicon Dioxide 66%
• Sub-10 Nm 33%
• Technology Challenges 100%
• Technology Requirements 100%

Material Science

• Charge Trapping 33%
• Dielectric Material 100%
• High-K Dielectric 100%
• Silicon Dioxide 66%

Engineering

• Dielectrics 100%
• Direct Tunneling 33%
• Gate Dielectric 33%
• Gate Length 33%
• Gate Stack 33%
• Power Requirement 33%
• Research Work 33%