TY - GEN
T1 - Leveraging dual-mode magnetic crossbar for ultra-low energy in-memory data encryption
AU - He, Zhezhi
AU - Angizi, Shaahin
AU - Parveen, Farhana
AU - Fan, Deliang
N1 - Publisher Copyright:
© 2017 ACM.
PY - 2017/5/10
Y1 - 2017/5/10
N2 - The logic-in-memory architecture is highly promising for high-throughput data-driven applications. This paper presents a novel dual-mode magnetic crossbar architecture consisting of perpendicularly cross-coupled magnetic racetrack nanowires, which could morph between non-volatile multi-bit racetrack memory mode and in-memory data encryption mode. The proposed magnetic crossbar is able to automatically perform parallel in-memory bit-wise XOR computations of the data stored in the racetrack memories with the help of magnetic coupling physics without complex peripheral circuits, which could be leveraged to design energy efficient in-memory data encryption engine. We employ Advanced Encryption Standard (AES) algorithm to elucidate the efficiency of the proposed design. The device-to-architecture level simulation results show that the proposed architecture can achieve 70% and 17.5% lower energy consumption compared to CMOSASIC and recent domain wall (DW) AES implementations, respectively. In addition, the AES encryption speed increases by 29.7% compared to the DW-AES implementation.
AB - The logic-in-memory architecture is highly promising for high-throughput data-driven applications. This paper presents a novel dual-mode magnetic crossbar architecture consisting of perpendicularly cross-coupled magnetic racetrack nanowires, which could morph between non-volatile multi-bit racetrack memory mode and in-memory data encryption mode. The proposed magnetic crossbar is able to automatically perform parallel in-memory bit-wise XOR computations of the data stored in the racetrack memories with the help of magnetic coupling physics without complex peripheral circuits, which could be leveraged to design energy efficient in-memory data encryption engine. We employ Advanced Encryption Standard (AES) algorithm to elucidate the efficiency of the proposed design. The device-to-architecture level simulation results show that the proposed architecture can achieve 70% and 17.5% lower energy consumption compared to CMOSASIC and recent domain wall (DW) AES implementations, respectively. In addition, the AES encryption speed increases by 29.7% compared to the DW-AES implementation.
KW - In-memory encryption
KW - Magnetic coupling
KW - Magnetic crossbar
UR - http://www.scopus.com/inward/record.url?scp=85021185931&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85021185931&partnerID=8YFLogxK
U2 - 10.1145/3060403.3060460
DO - 10.1145/3060403.3060460
M3 - Conference contribution
AN - SCOPUS:85021185931
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 83
EP - 88
BT - GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PB - Association for Computing Machinery
T2 - 27th Great Lakes Symposium on VLSI, GLSVLSI 2017
Y2 - 10 May 2017 through 12 May 2017
ER -