Low thermal budget processing for sequential 3-D IC fabrication

Bipin Rajendran, Rohit S. Shenoy, Daniel J. Witte, Nehal S. Chokshi, Robert L. DeLeon, Gary S. Tompa, R. Fabian W. Pease

Research output: Contribution to journalArticlepeer-review

42 Scopus citations

Abstract

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below.

Original languageEnglish (US)
Pages (from-to)707-714
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume54
Issue number4
DOIs
StatePublished - Apr 2007
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Keywords

  • CMOSFET
  • Integrated circuit fabrication
  • Laser annealing
  • Low-pressure chemical vapor deposition (LPCVD)

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