Low thermal budget processing for sequential 3-D IC fabrication

Bipin Rajendran; Rohit S. Shenoy; Daniel J. Witte; Nehal S. Chokshi; Robert L. DeLeon; Gary S. Tompa; R. Fabian W. Pease

doi:10.1109/TED.2007.891300

Low thermal budget processing for sequential 3-D IC fabrication

Bipin Rajendran, Rohit S. Shenoy, Daniel J. Witte, Nehal S. Chokshi, Robert L. DeLeon, Gary S. Tompa, R. Fabian W. Pease

Research output: Contribution to journal › Article › peer-review

58 Scopus citations

Abstract

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below.

Original language	English (US)
Pages (from-to)	707-714
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	54
Issue number	4
DOIs	https://doi.org/10.1109/TED.2007.891300
State	Published - Apr 2007
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Keywords

CMOSFET
Integrated circuit fabrication
Laser annealing
Low-pressure chemical vapor deposition (LPCVD)

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10.1109/TED.2007.891300

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@article{6e56a1456d254cc597e01020831f5ca3,

title = "Low thermal budget processing for sequential 3-D IC fabrication",

abstract = "Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below.",

keywords = "CMOSFET, Integrated circuit fabrication, Laser annealing, Low-pressure chemical vapor deposition (LPCVD)",

author = "Bipin Rajendran and Shenoy, {Rohit S.} and Witte, {Daniel J.} and Chokshi, {Nehal S.} and DeLeon, {Robert L.} and Tompa, {Gary S.} and Pease, {R. Fabian W.}",

note = "Funding Information: Manuscript received September 1, 2006; revised December 11, 2006. This work was supported in part by the Office of Naval Research under Award N00014-01-1-0741 and in part by the Defense Advanced Research Projects Agency under Award N66001-04-1-8916. The review of this paper was arranged by Editor V. R. Rao.",

year = "2007",

month = apr,

doi = "10.1109/TED.2007.891300",

language = "English (US)",

volume = "54",

pages = "707--714",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

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T1 - Low thermal budget processing for sequential 3-D IC fabrication

AU - Rajendran, Bipin

AU - Shenoy, Rohit S.

AU - Witte, Daniel J.

AU - Chokshi, Nehal S.

AU - DeLeon, Robert L.

AU - Tompa, Gary S.

AU - Pease, R. Fabian W.

N1 - Funding Information: Manuscript received September 1, 2006; revised December 11, 2006. This work was supported in part by the Office of Naval Research under Award N00014-01-1-0741 and in part by the Defense Advanced Research Projects Agency under Award N66001-04-1-8916. The review of this paper was arranged by Editor V. R. Rao.

PY - 2007/4

Y1 - 2007/4

N2 - Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below.

AB - Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below.

KW - CMOSFET

KW - Integrated circuit fabrication

KW - Laser annealing

KW - Low-pressure chemical vapor deposition (LPCVD)

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 4

ER -

Low thermal budget processing for sequential 3-D IC fabrication

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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