Low voltage SILC analysis for high-k/metal gate dielectrics

N. Rahim, D. Misra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Conduction behavior of multi-layer structure of metal/high-k/interfacial layer gate stacks was investigated before and after constant voltage stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-S1LC) was analyzed systematically with gate stacks of different interfacial layer thicknesses and SiO2-only devices of identical processing condition. Based on the results of defect generation sensed by the LV-SILC, it is observed that discrete levels of trap generation in the interfacial layer primarily causes low voltage SILC in metal/high-k gate stacks and initiates the gate stack breakdown.

Original languageEnglish (US)
Title of host publicationECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages283-287
Number of pages5
Edition1
DOIs
StatePublished - Dec 1 2009
EventInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting - San Francisco, CA, United States
Duration: May 24 2009May 29 2009

Publication series

NameECS Transactions
Number1
Volume19
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting
CountryUnited States
CitySan Francisco, CA
Period5/24/095/29/09

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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