@inproceedings{2d2e67f2a2524e9eb3cb94ca611915ae,
title = "Low voltage SILC analysis for high-k/metal gate dielectrics",
abstract = "Conduction behavior of multi-layer structure of metal/high-k/interfacial layer gate stacks was investigated before and after constant voltage stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-S1LC) was analyzed systematically with gate stacks of different interfacial layer thicknesses and SiO2-only devices of identical processing condition. Based on the results of defect generation sensed by the LV-SILC, it is observed that discrete levels of trap generation in the interfacial layer primarily causes low voltage SILC in metal/high-k gate stacks and initiates the gate stack breakdown.",
author = "N. Rahim and D. Misra",
year = "2009",
doi = "10.1149/1.3118955",
language = "English (US)",
isbn = "9781566777094",
series = "ECS Transactions",
publisher = "Electrochemical Society Inc.",
number = "1",
pages = "283--287",
booktitle = "ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5",
edition = "1",
note = "International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment - 215th ECS Meeting ; Conference date: 24-05-2009 Through 29-05-2009",
}