LT-PIM: An LUT-Based Processing-in-DRAM Architecture with RowHammer Self-Tracking

Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Herein, we propose LT-PIM as a Lookup Table-based Processing-In-Memory architecture leveraging the high density of DRAM to enable massively parallel and flexible computation. LT-PIM supports lookup table queries to execute complex arithmetic operations, such as multiplication via only memory read operation. In addition, LT-PIM enables bulk bit-wise in-memory logic by elevating the analog operation of the DRAM sub-array to implement Boolean functions between operands in the same bit-line. With this, LT-PIM enables a complete and inexpensive in-DRAM RowHammer (RH) self-tracking approach. Our results demonstrate that LT-PIM achieves ∼70% higher energy efficiency than the fastest charge-sharing-based designs and ∼32% over the best LUT-based designs. As for the RH self-tracking, with a worst-case slowdown of ∼0.2%, LT-PIM archives up to ∼80% energy-saving over the best designs.

Original languageEnglish (US)
Pages (from-to)141-144
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - 2022

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


  • DRAM
  • Processing-in-memory
  • look-up table
  • row hammer


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