Maximizing Sub-Array Resource Utilization in Digital Processing-in-Memory: A Versatile Hardware-Aware Approach

In digital Processing-in-Memory (PIM) architectures for Artificial Intelligence (AI) acceleration, efficient resource utilization and sub-array level computation reuse remain critical challenges. To address this, mapping strategies such as Bit-Parallel Mapping (BPM) and Bit-Serial Mapping (BSM) have been proposed, each offering distinct latency and parallelism trade-offs. Despite demonstrating promising results in their respective applications, these mapping schemes are hindered by memory inefficiencies. Such wastage reduces the effective memory utilization, limits the number of executable operations, and constrains overall computational throughput. To overcome these limitations, this paper introduces a novel mapping approach, termed U-shaped Mapping (USM), wherein results are organized in a U-shaped pattern within memory arrays. This structure enables efficient data reuse, leading to fast, area-efficient, and high-throughput PIM operations. The proposed technique enables computation over larger input sizes by efficiently utilizing previously unused memory regions. This results in a significant increase in the number of operations that can be executed within a fixed hardware footprint. Experimental evaluation shows that the USM achieves up to 2.33 × reduction in EDP and 2.78 × improvement in throughput compared to the BSM approach. These improvements confirm USM's suitability for optimizing computational efficiency and resource usage in energy- and area-constrained edge devices.