Abstract
A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| Publisher | IEEE |
| Pages | 384-385 |
| Number of pages | 2 |
| ISBN (Print) | 0769501044 |
| State | Published - Dec 1 1999 |
| Event | Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Duration: Mar 4 1999 → Mar 6 1999 |
Other
| Other | Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) |
|---|---|
| City | Ann Arbor, MI, USA |
| Period | 3/4/99 → 3/6/99 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering