Memory chip BIST architecture

Jacob Savir

Memory chip BIST architecture

Jacob Savir

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.

Original language	English (US)
Title of host publication	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publisher	IEEE
Pages	384-385
Number of pages	2
ISBN (Print)	0769501044
State	Published - 1999
Event	Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Duration: Mar 4 1999 → Mar 6 1999

Publication series

Name	Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)	1066-1395

Other

Other	Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
City	Ann Arbor, MI, USA
Period	3/4/99 → 3/6/99

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@inproceedings{dd25188489524fb3a43b8c29f3e22983,

title = "Memory chip BIST architecture",

abstract = "A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.",

author = "Jacob Savir",

year = "1999",

language = "English (US)",

isbn = "0769501044",

series = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

publisher = "IEEE",

pages = "384--385",

booktitle = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

note = "Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) ; Conference date: 04-03-1999 Through 06-03-1999",

}

TY - GEN

T1 - Memory chip BIST architecture

AU - Savir, Jacob

PY - 1999

Y1 - 1999

N2 - A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.

AB - A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.

UR - http://www.scopus.com/inward/record.url?scp=0033355867&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033355867&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0033355867

SN - 0769501044

T3 - Proceedings of the IEEE Great Lakes Symposium on VLSI

SP - 384

EP - 385

BT - Proceedings of the IEEE Great Lakes Symposium on VLSI

PB - IEEE

T2 - Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)

Y2 - 4 March 1999 through 6 March 1999

ER -

Memory chip BIST architecture

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

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