Memory chip BIST architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages384-385
Number of pages2
ISBN (Print)0769501044
StatePublished - Dec 1 1999
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: Mar 4 1999Mar 6 1999

Other

OtherProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period3/4/993/6/99

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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