Modeling and simulation of drain current 1/f noise in high-κ based n-MOSFETs

This work summarizes the results of modeling and simulation of drain current low-frequency (1/f) noise in devices with Hf-based dielectrics as gate oxides. The proposed physics-based model is based on trap-assisted thermally activated tunneling in both the interfacial layer (IL) and the high-κ layer. The model proposed considers not only the location of the traps in the oxide but also the energy level in the interfacial and the high-κ layer The critical factors which influence the drain current noise such as the tunneling time constant, and attenuation parameter are estimated The estimated values are used to model drain current 1/f noise The simulation results agree well with the experimental results, with errors in the acceptable margin levels. The results show the importance of interfacial layer and the temperature in determining the noise levels in high-κ dielectrics.