Module Level Weighted Random Patterns

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature is collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead.

Original languageEnglish (US)
Pages (from-to)283-287
Number of pages5
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume10
Issue number3
DOIs
StatePublished - Jan 1 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Module Level Weighted Random Patterns'. Together they form a unique fingerprint.

Cite this