The paper describes a module level self-test architecture that uses weighted random patterns. A pseudo-random pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature is collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings of the Asian Test Symposium|
|State||Published - Dec 1 1995|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering