MR-PIPA: An Integrated Multilevel RRAM (HfOx)-Based Processing-In-Pixel Accelerator

Minhaz Abedin, Arman Roohi, Maximilian Liehr, Nathaniel Cady, Shaahin Angizi

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

This work paves the way to realize a processing-in-pixel (PIP) accelerator based on a multilevel HfOx resistive random access memory (RRAM) as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing at edge devices. The proposed design intrinsically implements and supports a coarse-grained convolution operation in low-bit-width neural networks (NNs) leveraging a novel compute-pixel with nonvolatile weight storage at the sensor side. Our evaluations show that such a design can remarkably reduce the power consumption of data conversion and transmission to an off-chip processor maintaining accuracy compared with the recent in-sensor computing designs. Our proposed design, namely an integrated multilevel RRAM (HfOx)-based processing-in-pixel accelerator (MR-PIPA), achieves a frame rate of 1000 and efficiency of 1.89 TOp/s/W, while it substantially reduces data conversion and transmission energy by 84% compared to a baseline at the cost of minor accuracy degradation.

Original languageEnglish (US)
Pages (from-to)59-67
Number of pages9
JournalIEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Volume8
Issue number2
DOIs
StatePublished - Dec 1 2022

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Accelerator
  • convolutional neural network (CNN)
  • nonvolatile memory (NVM)
  • processing-in-pixel (PIP)
  • resistive random access memory (RRAM)

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