Neuromorphic Accelerator for Deep Spiking Neural Networks with NVM Crossbar Arrays

Shruti R. Kulkarni, Shihui Yin, Jae Sun Seo, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a scalable digital hardware accelerator based on non-volatile memory arrays capable of realizing deep convolutional spiking neural networks (SNNs). Our design studies are conducted using a compact model for spin-transfer torque random access memory (STT-RAM) devices. Large networks are realized by tiling multiple cores which communicate by transmitting spike packets via an on-chip routing network. Compared to an equivalent SRAM based core design, we show that the STT-RAM based design achieves nearly 15X higher GSOPS (Synaptic Operations per Second) per Watt per mm2 making it a promising platform for realizing systems with significant area and power limitations.

Original languageEnglish (US)
Title of host publication2022 IEEE International Conference on Emerging Electronics, ICEE 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665491853
DOIs
StatePublished - 2022
Externally publishedYes
Event2022 IEEE International Conference on Emerging Electronics, ICEE 2022 - Bangalore, India
Duration: Dec 11 2022Dec 14 2022

Publication series

Name2022 IEEE International Conference on Emerging Electronics, ICEE 2022

Conference

Conference2022 IEEE International Conference on Emerging Electronics, ICEE 2022
Country/TerritoryIndia
CityBangalore
Period12/11/2212/14/22

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Instrumentation

Keywords

  • Spiking neural networks
  • Spin Transfer Torque RAM
  • neuromorphic accelerators
  • non-volatile memory

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