Novel biomimetic Si devices for neuromorphic computing architecture

U. Ganguly, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Neuromorphic computing requires low-power devices and circuits in cross-point architecture. On-chip learning is a significant challenge that requires the implementation of learning rules like spike-timing-dependent plasticity (STDP)—a method that modifies synaptic strength depending upon the time correlation between the presynaptic and postsynaptic neuron spikes in a specific function. To implement this capability in phase-change memory (PCM) or resistance RAM (RRAM)-based cross-point arrays, two schemes have been proposed in the literature where the time correlations are captured by an address event representation scheme using an universal bus or superposition of long custom waveforms. In comparison, in biology, the pulses are sharp and the time correlation information is processed at the synapse by the natural dynamics of the synapse. These are attractive attributes forminimizing power and complexity/area. Another challenge is realizing an area- and power-efficient implementation of the electronic neuron. A leaky integrate-and-fire (LIF) neuron has been implemented using analog and digital circuits which are highly power and area inefficient. To improve area and power efficiency, we have recently proposed: (i) A Si diode-based synaptic device where the charge carrier internal dynamics is used to capture the time correlation based on sharp pulses (100×sharper than custom waveforms to improve energy per spike) which can operate at 103–106 times faster than biology (providing accelerated learning) and (ii) A compact Si neuronal device that has a 60× area and 5× power benefit compared to analog implementation of neurons. These are novel devices that are based on SiGe CMOS technology, and they are highly manufacturable. The synaptic devices are based on natural transients of the impact ionization-based n+ p n+ diode (I-NPN diode). STDP and Hebbian learning rules have been implemented. The neuron requires further modification of the I-NPN diode requiring a gating structure and some simple circuits. A leaky integrateand- fire (LIF) neuron has also been demonstrated. Based on their device-level area and power efficiency, system-level power and area of neural networks will be highly enhanced.

Original languageEnglish (US)
Title of host publicationCognitive Systems Monographs
PublisherSpringer Verlag
Pages151-174
Number of pages24
DOIs
StatePublished - Jan 1 2017
Externally publishedYes

Publication series

NameCognitive Systems Monographs
Volume31
ISSN (Print)1867-4925
ISSN (Electronic)1867-4933

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Computer Science(all)

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