Novel pipelined architecture for efficient evaluation of the square root using a modified non-restoring algorithm

Imtiaz Sajid, M. M. Ahmed, Sotirios G. Ziavras

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

The square root is a basic arithmetic operation in image and signal processing. We present a novel pipelined architecture to implement N-bit fixed-point square root operation on an FPGA using a non-restoring pipelined algorithm that does not require floating-point hardware. Pipelining hazards in its hardware realization are avoided by modifying the classic non-restoring algorithm, thus resulting in a 13% improved latency. Furthermore, the proposed architecture is flexible allowing modification as per individual application needs. It is demonstrated that the proposed architecture is approximately four times faster than its popular counterparts and at the same time it consumes 50% less energy for envelope detection at 268 MHz sampling rate.

Original languageEnglish (US)
Pages (from-to)157-166
Number of pages10
JournalJournal of Signal Processing Systems
Volume67
Issue number2
DOIs
StatePublished - May 1 2012

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modeling and Simulation
  • Hardware and Architecture

Keywords

  • Field-Programmable Gate Array (FPGA)
  • Fixed-point arithmetic
  • Non-restoring algorithm
  • Pipelining
  • Square root

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