Abstract
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called 'broad-side' since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broad-side delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy.
| Original language | English (US) |
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| Pages | 284-290 |
| Number of pages | 7 |
| State | Published - 1994 |
| Externally published | Yes |
| Event | Proceedings of the 12th IEEE VLSI Test Symposium - Cherry Hill, NJ, USA Duration: Apr 25 1994 → Apr 28 1994 |
Other
| Other | Proceedings of the 12th IEEE VLSI Test Symposium |
|---|---|
| City | Cherry Hill, NJ, USA |
| Period | 4/25/94 → 4/28/94 |
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering