This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to `go after' the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.
|Original language||English (US)|
|Number of pages||9|
|Journal||Proceedings of the Asian Test Symposium|
|State||Published - Dec 1 1997|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering