On-Chip Weighted Random Patterns

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Abstract

Even though there has been a considerable effort in proposing weighted random pattern testing schemes over the years, insufficient attention has been devoted to their implementation. This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.

Original languageEnglish (US)
Pages (from-to)41-50
Number of pages10
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume13
Issue number1
DOIs
StatePublished - Jan 1 1998

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Keywords

  • BIST
  • Detection probability
  • LSSD
  • SRL
  • Signal probability
  • WRP

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