Abstract
In this paper, we present a methodology of choosing an NPN selector (1S) for a given memory element (1M) to form a cross point (consisting of the memory element in series with the selector - 1S1M) based on the overall array power efficiency requirements. This methodology is based on extensive TCAD simulations that show excellent match with our experimentally demonstrated n+/p/n+ epitaxial Si punch-through diode as selector (NPN selector) for symmetric bipolar resistive RAM. Using a TCAD validated circuit model of the NPN selector, we derive an equivalent circuit model for the cross point. For an exemplary selector design, our model suggests that the power Pxp dissipated in the cross point during set operation obeys the relationship Pxp ⋉ Vset0.5Iset1.25, even though the power dissipated in the memory element Pmemory is V setIset. This shows that lowering the set current I set of the memory element leads to a larger reduction in array power than lowering the set voltage Vset.
Original language | English (US) |
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Article number | 6620975 |
Pages (from-to) | 1178-1184 |
Number of pages | 7 |
Journal | IEEE Transactions on Nanotechnology |
Volume | 12 |
Issue number | 6 |
DOIs | |
State | Published - 2013 |
Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering
Keywords
- Bipolar resistive RAM (RRAM)
- Compact circuit model
- Cross-point memory array
- NPN selector
- Punch-through bipolar selector device
- Resistance ratio