On shrinking wide compressors

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISRs) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Wide MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking a MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method.

Original languageEnglish (US)
Pages108-117
Number of pages10
StatePublished - Jan 1 1995
Externally publishedYes
EventProceedings of the 13th IEEE VLSI Test Symposium - Princeton, NJ, USA
Duration: Apr 30 1995May 3 1995

Other

OtherProceedings of the 13th IEEE VLSI Test Symposium
CityPrinceton, NJ, USA
Period4/30/955/3/95

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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