Abstract
Testing and characterization of analog circuits is a very important task in the VLSI manufacturing process. However, no efficient methodology exists on how to effectively model and characterize the various faults, and even how to detect their existence. Neural networks have been successfully applied to various pattern recognition problems. In this paper, the amplitude and temporal characteristics of the good circuit response are used to train a neural network, so that it is able to distinguish between different faulty circuit responses. A Time-Delay Neural Network (TDNN) is proposed as a possible vehicle for performing the test and diagnosis.
Original language | English (US) |
---|---|
Pages (from-to) | 338-343 |
Number of pages | 6 |
Journal | Proceedings of the Asian Test Symposium |
State | Published - 2001 |
Event | Proceedings of the 10th Asian Test Symposium - Kyoto, Japan Duration: Nov 19 2001 → Nov 21 2001 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Keywords
- Characterization
- Fault detection
- Neural network
- System on a chip