On the architectural requirements for efficient execution of graph algorithms

David A. Bader, Guojing Cong, John Feo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

71 Scopus citations

Abstract

Combinatorial problems such as those from graph theory pose serious challenges for parallel machines due to non-contiguous, concurrent accesses to global data structures with low degrees of locality. The hierarchical memory systems of symmetric multiprocessor (SMP) clusters optimize for local, contiguous memory accesses, and so are inefficient platforms for such algorithms. Few parallel graph algorithms outperform their best sequential implementation on SMP clusters due to long memory latencies and high synchronization costs. In this paper, we consider the performance and scalability of two graph algorithms, list ranking and connected components, on two classes of sharedmemory computers: symmetric multiprocessors such as the Sun Enterprise servers and multithreaded architectures (MTA) such as the Cray MTA-2. While previous studies have shown that parallel graph algorithms can speedup on SMPs, the systems' reliance on cache microprocessors limits performance. The MTA 's latency tolerant processors and hardware support for fine-grain synchronization makes performance a function of parallelism. Since parallel graph algorithms have an abundance of parallelism, they perform and scale significantly better on the MTA. We describe and give a performance model for each architecture. We analyze the performance of the two algorithms and discuss how the features of each architecture affects algorithm- development, ease of programming, performance, and scalability.

Original languageEnglish (US)
Title of host publicationProceedings - 2005 International Conference on Parallel Processing
Pages547-556
Number of pages10
DOIs
StatePublished - 2005
Externally publishedYes
Event2005 International Conference on Parallel Processing - Oslo, Norway
Duration: Jun 14 2005Jun 17 2005

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume2005
ISSN (Print)0190-3918

Conference

Conference2005 International Conference on Parallel Processing
Country/TerritoryNorway
CityOslo
Period6/14/056/17/05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • General Engineering

Keywords

  • Connected Components
  • Graph Algorithms
  • List ranking
  • Multithreading
  • Shared memory

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