Abstract
This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%.
Original language | English (US) |
---|---|
Pages (from-to) | 296-299 |
Number of pages | 4 |
Journal | Proceedings of the Asian Test Symposium |
State | Published - 1997 |
Event | Proceedings of the 1997 6th Asian Test Symposium - Akita, Jpn Duration: Nov 17 1997 → Nov 19 1997 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering