Optimized scaling of diode array design for 32NM node phase change memory

Kailiang Lu; Bipin Rajendran; Thomas D. Happ; Ricky M.Y. Ng; Hsiang Lan Lung; Chung Lam; Mansun Chan

doi:10.1109/VTSA.2008.4530833

Optimized scaling of diode array design for 32NM node phase change memory

Kailiang Lu
, Bipin Rajendran
, Thomas D. Happ
, Ricky M.Y. Ng
, Hsiang Lan Lung
, Chung Lam
, Mansun Chan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English (US)
Title of host publication	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Pages	134-135
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2008.4530833
State	Published - 2008
Externally published	Yes
Event	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China Duration: Apr 21 2008 → Apr 23 2008

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Other

Other	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	4/21/08 → 4/23/08

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/VTSA.2008.4530833

Cite this

Lu, K., Rajendran, B., Happ, T. D., Ng, R. M. Y., Lung, H. L., Lam, C., & Chan, M. (2008). Optimized scaling of diode array design for 32NM node phase change memory. In 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA (pp. 134-135). Article 4530833 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2008.4530833

@inproceedings{7c918a6ca8854e5191a3cca3795d351a,

title = "Optimized scaling of diode array design for 32NM node phase change memory",

author = "Kailiang Lu and Bipin Rajendran and Happ, \{Thomas D.\} and Ng, \{Ricky M.Y.\} and Lung, \{Hsiang Lan\} and Chung Lam and Mansun Chan",

year = "2008",

doi = "10.1109/VTSA.2008.4530833",

language = "English (US)",

isbn = "9781424416158",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

pages = "134--135",

booktitle = "2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA",

note = "2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA ; Conference date: 21-04-2008 Through 23-04-2008",

}

Lu, K, Rajendran, B, Happ, TD, Ng, RMY, Lung, HL, Lam, C & Chan, M 2008, Optimized scaling of diode array design for 32NM node phase change memory. in 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA., 4530833, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, pp. 134-135, 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA, Hsinchu, Taiwan, Province of China, 4/21/08. https://doi.org/10.1109/VTSA.2008.4530833

Optimized scaling of diode array design for 32NM node phase change memory. / Lu, Kailiang; Rajendran, Bipin; Happ, Thomas D. et al.
2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA. 2008. p. 134-135 4530833 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Optimized scaling of diode array design for 32NM node phase change memory

AU - Lu, Kailiang

AU - Rajendran, Bipin

AU - Happ, Thomas D.

AU - Ng, Ricky M.Y.

AU - Lung, Hsiang Lan

AU - Lam, Chung

AU - Chan, Mansun

PY - 2008

Y1 - 2008

UR - https://www.scopus.com/pages/publications/49049084423

UR - https://www.scopus.com/pages/publications/49049084423#tab=citedBy

U2 - 10.1109/VTSA.2008.4530833

DO - 10.1109/VTSA.2008.4530833

M3 - Conference contribution

AN - SCOPUS:49049084423

SN - 9781424416158

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SP - 134

EP - 135

BT - 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA

T2 - 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA

Y2 - 21 April 2008 through 23 April 2008

ER -

Optimized scaling of diode array design for 32NM node phase change memory

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Cite this