Optimizing energy consumption and parallel performance for static and dynamic betweenness centrality using GPUs

Adam McLaughlin, Jason Riedy, David A. Bader

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Applications of high-performance graph analysis range from computational biology to network security and even transportation. These applications often consider graphs under rapid change and are moving beyond HPC platforms into energy-constrained embedded systems. This paper optimizes one successful and demanding analysis kernel, betweenness centrality, for NVIDIA GPU accelerators in both environments. Our algorithm for static analysis is capable of exceeding 2 million traversed edges per second per watt (MTEPS/W). Optimizing the parallel algorithm and treating the dynamic problem directly achieves a 6.9× average speed-up and 83% average reduction in energy consumption.

Original languageEnglish (US)
Title of host publication2014 IEEE High Performance Extreme Computing Conference, HPEC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479962334
DOIs
StatePublished - Feb 11 2014
Externally publishedYes
Event2014 IEEE High Performance Extreme Computing Conference, HPEC 2014 - Waltham, United States
Duration: Sep 9 2014Sep 11 2014

Publication series

Name2014 IEEE High Performance Extreme Computing Conference, HPEC 2014

Other

Other2014 IEEE High Performance Extreme Computing Conference, HPEC 2014
Country/TerritoryUnited States
CityWaltham
Period9/9/149/11/14

All Science Journal Classification (ASJC) codes

  • Software

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