Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines

Keyphrases

• Field Programmable Gate Arrays 100%
• Array-based 100%
• Compute Engine 100%
• Sparse Matrices 100%
• Configurable Computing 100%
• Parallel LU Factorization 100%
• Parallel Machines 66%
• LU Factorization 66%
• Performance Improvement 33%
• Moore's Law 33%
• Hardware Resources 33%
• Silicon Technology 33%
• Linear Equations 33%
• Large Systems 33%
• Computing Platform 33%
• Hardware Design 33%
• Network of Workstations 33%
• Compute-intensive Applications 33%
• Performance Results 33%
• Programmable System-on-Chip (PSoC) 33%
• System of Linear Equations 33%
• Development Board 33%
• Microarray Technology 33%
• Configurable Processor 33%
• Multiple Instances 33%
• Silicon chip 33%
• Application-specific Hardware 33%
• Soft IP 33%

Computer Science

• Field Programmable Gate Arrays 100%
• Linear Equation 66%
• Parallel Machine 66%
• Computing Platform 33%
• Moore's Law 33%
• Hardware Resource 33%
• Supercomputer 33%
• Intensive Application 33%
• Hardware Design 33%
• Configurable Processor 33%
• Development Board 33%
• Multiple Instance 33%

Engineering

• Field Programmable Gate Arrays 100%
• Linear Equation 100%
• Engineering 50%
• Moore's Law 50%
• Silicon Technology 50%
• Field Programmable Gate Array Technology 50%
• Development Board 50%