Parallel solution of Newton's power flow equations on configurable chips

Keyphrases

• Multiprocessor 100%
• LU Factorization 100%
• Jacobian Matrix 100%
• Newton's Method 100%
• Power Flow Equation 100%
• Newton Power Flow 100%
• Parallel Solution 100%
• Power Grid 50%
• Turnaround Time 50%
• Field Programmable Gate Arrays 50%
• High Performance 50%
• Silicon Technology 50%
• Parallel Implementation 50%
• Large Systems 50%
• Computing Platform 50%
• Shared Memory 50%
• Computing Paradigm 50%
• Application Specific Integrated Circuits 50%
• Microprocessor 50%
• Partitioning Scheme 50%
• Performance Results 50%
• Programmable System-on-Chip (PSoC) 50%
• Newton-Raphson Method 50%
• Configurable Computing 50%
• Memory Requirements 50%
• Non-axisymmetric 50%
• Single chip 50%
• Power Flow Problem 50%
• Efficient Parallelisation 50%
• Cost-effective Approach 50%
• AC Power Flow 50%
• Local Quadratic Convergence 50%
• Array Devices 50%
• US Power 50%
• Online Operations 50%
• Robust Approach 50%
• Integrated Circuit Design 50%
• Power Test 50%
• Programmable Logic 50%

Computer Science

• multi-processor 100%
• Jacobian Matrix 100%
• Newton's Method 100%
• Parallel Solution 100%
• Effective Approach 50%
• Computing Platform 50%
• computing paradigm 50%
• Field Programmable Gate Arrays 50%
• Shared Memories 50%
• Parallelization 50%
• Application Specific Integrated Circuit 50%
• Good Performance 50%
• Parallel Implementation 50%
• single-chip 50%
• Memory Requirement 50%
• Newton-Raphson Method 50%
• Robust Approach 50%
• Programmable Logic 50%
• Integrated Circuit Design 50%